(1) Field of the Invention
The present invention relates to a process used to fabricate a dynamic random access memory, (DRAM), cell, on a semiconductor substrate, and more specifically to a new design, and a new fabrication process, used to optimize the process and layout, of contact holes used for DRAM capacitor and bit line structures.
(2) Description of the Prior Art
In order to satisfy demands for high density DRAM semiconductor chips, micro-miniaturization, or the use of sub-micron features, used for DRAM designs, are employed. The attainment of micro-miniaturazation, or sub-micron features, has been mainly accomplished by advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. In addition the development of more advanced dry etching tools and etch recipes, have allowed the sub-micron images in overlying photoresist layers to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices.
However to achieve DRAM cell densities of 1 gigabit, or greater, new designs, in addition to process enhancements, may be needed. One area of concern, using micro-miniaturization to achieve device density demands, is the use of smaller contact holes. The use of smaller contact holes is needed so that the minimum spacing between contact holes, is not decreased to a level in which photolithographic procedures, such as exposure and photoresist development, create risks in terms of yield. Therefore in order to achieve desired device densities, and not to enter beyond the minimum design spacing between contact holes, the size of the contact holes have to be decreased. Therefore conductive landing plugs, used to fill these smaller contact holes, are now more resistive, deleteriously influencing performance.
This invention will offer a new layout or design, as well as a new process, for DRAM contact holes, used for capacitor and bit line structures. An interlaced mask design and layout, using a first mask for a bit line contact hole, placed in a first cell, and capacitor node contact hole, placed in a neighboring second cell, followed by the use of a second mask, placing a bit line contact hole in the first cell, while placing a capacitor node contact hole in the neighboring second cell, allows larger contact hole sizes to be used, without sacrificing device density. The minimum spacing requirement, which is a concern when using a single mask, and a single photoresist layer, to create contact holes for both capacitor and bit line structures, in a specific cell, is not relevant in this invention. This invention features forming a combination of bit line contact hole images, and capacitor node contact hole images, in a thin polysilicon layer, using a first mask and a first photoresist layer, and then forming a second combination of bit line contact hole images and capacitor node contact hole image in the same thin polysilicon layer, using a second mask and a second photoresist layer. The patterned thin polysilicon layer is then used as a mask to open the desired contact holes, in an insulator layer, exposing active regions in the semiconductor substrate. The minimum spacing requirement, used between features in a single photoresist layer, is not relevant since the masking layer used for contact hole definition was formed in a single polysilicon layer, using two separate masks. Therefore the larger contact holes allow the use of larger conductive landing plugs, resulting in the use of easier process sequence, limited not by minimum spacing requirements, but only limited by layer to layer overlay.
Prior art, such as Ham, in U.S. Pat. No. 5,573,634, describes a method for forming contact holes in an insulator layer by double exposure of a single photoresist layer, using two masks. However that prior art does not show the use of two photoresist layers, and the use of two masks, resulting in the creation of the desired layout in a thin polysilicon layer, and than using the patterned polysilicon layer as the etch mask for contact hole definition.